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school and education

CET CODE: LIET

bobbara jaya lakshmi

bobbara jaya lakshmi

bobbara jaya lakshmi
Female
04/24/1994
9052674097
i am jaya
02/09/2018
Assistant professor
1 YEAR AS TEACHING ASSISTANT
LT0464
M.Tech
vlsi
Electronics and communication Engineering

IEEE IWEEK WORKSHOP ON ADVANCED ANTENNAS AND APPLICATIONS IN MVGR COLLEGE OF ENGINEERING 

international journal of innovative technology &exploring engineering

"implementation of low power high performance adder circuits

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Design of High Speed and Low Power Multiplier using Dual Mode Square adder

Abstract Adders are basic building blocks in analog and digital circuits for implementing arithmetic operations. These are widely used in arithmetic systems, graphic related applications and DSP oriented systems etc. Different techniques are reported in open literature to obtain high speed, less area and low power dissipation. Dual Mode Logic (DML) and Dual Mode Addition (DMADD) techniques can be used to achieve low power and high speed addition. Adders are crucial in effective implementation of multipliers. In this paper braun multiplier is designed using dual mode square adder. The full adder used in dual mode square adder is SERF adder, which achieves high speed, less area and consumes low power compared to conventional full adder. Power consumption is reduced by 63.54% and speed is increased by 90% for braun multiplier using dual mode square adder. Multiplier is implemented using mentor graphics tools in 130 nm technology.

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