CET CODE: LIET

SCI

·      S. K. Beura, B. P. Devi, P. Saha, and P. K. Meher, (2024) "Design of a Novel Inexact 4:2 Compressor and its Placement in the Partial Product Array for Area, Delay, and Power E?icient Inexact Signed Multiplier", in Circuit System and Signal Processing (Springer), pp 1-27 https://doi.org/10.1007/s00034-024-02630-4

·     S. K. Beura, S. M. Mahanta, B. P. Devi and P. Saha, (2023), Inexact Radix-4 Booth Multipliers based on New Partial Product Generation Scheme for Image Multiplication, Integration VLSI Journal (Elsevier), vol. 94, pp 102096. https://doi.org/10.1016/j.vlsi.2023.102096.

·       G. Palai, S.K. Beura, N. Gupta, R. Sinha, (2017) Optical MUX/DEMUX using 3D photonic crystal structure: A future application of silicon photonics, Optik, Volume 128, Pages 224-227.

Scopus

·        S K Beura, R U Ahmed, B P Devi, P Saha, (2021) "On The Implementation of Densely Packed Decimal Number System based Adder: Prospects and Challenges" ELECTRONICS 25 (1), 20-31.

·        S K Beura, A A Jawale, B P Devi, and P Saha, (2020). "On the Implementation of Multi-bit Inexact Adder Cells and Application towards Image Denoising." ELECTRONICS, 24(1).

G. Palai, & S. K. Beura, (2013). High reflectance of semiconductor-glass grating for SOI application. Trends in Opto-Electro & Optical Communications, 3, 9-12.

S. K. Beura, G. A. Prabhakar, S. M. Mahanta, B. P. Devi, and P. Saha, "Design and Analysis of Inexact 3:2 Compressor-based Radix-4 Multiplier towards Image Multiplication," 2021 12th International

Conference on Computing Communication and Networking Technologies (ICCCNT), Kharagpur, India, 2021, pp. 01-06, doi: 10.1109/ICCCNT51525.2021.9579872.

S. K. Beura, J. Samanta, B. P. Devi, and P. Saha, "Floating Point Adder using Inexact Mantissa Adder," 2023 4th International Conference on Computing and Communication Systems (I3CS2023), NEHU Shillong, India, 2023, pp. 1-5, doi: 10.1109/I3CS58314.2023.10127550.

   ·       Certifications (Academic/industrial):

        Advanced Post Graduate Diploma in VLSI Design from Semi-Conductor Laboratory, Chandigarh. Certificate is issued by the Semi-Conductor Laboratory (SCL),
        Department of Space, Chandigarh, India.

·       Achievements

·       Session Chair in 1st International Conference on Computing for Science, Engineering and Artificial Intelligence (CSEAi - 2023) at LIET.

·       Reviewer in journals (IEEE TCAS-I, CSSP, Electronics, JCSC) and conferences (ISCAS, ICEPE, CSEAi).

·       Presented paper in research conclave-2023 at NIT Meghalaya and won the 1st prize.